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SX1211
WIRELESS & SENSING
Table 14: Data Operation Mode Selection
MCParam_Data_mode
00
01
1x
Data Operation Mode
Continuous
Buffered
Packet
Each of these data operation modes is described fully in the following sections.
5.2. Control Block Description
5.2.1. SPI Interface
5.2.1.1. Overview
As illustrated in the Figure 26 below, the SX1211’s SPI interface consists of two sub blocks:
SPI Config : used in all data operation modes to read and write the configuration registers which control all the
parameters of the chip (operating mode, bit rate, etc...)
SPI Data : used in Buffered and Packet mode to write and read data bytes to and from the FIFO. (FIFO
interrupts can be used to manage the FIFO content.)
SX1211
Config.
Registers
SPI
CONFIG
(slave)
NSS_CONFIG
MOSI
MISO
SCK
NSS_CONFIG
MOSI
MISO
SCK
NSS_DATA
FIFO
SPI
DATA
(slave)
NSS_DATA
μC
(master)
Figure 26: SPI Interface Overview and uC Connections
Both interfaces are configured in slave mode whilst the uC is configured as the master. They have separate
selection pins (NSS_CONFIG and NSS_DATA) but share the remaining pins:
SCK (SPI Clock): clock signal provided by the uC
MOSI (Master Out Slave In): data input signal provided by the uC
MISO (Master In Slave Out): data output signal provided by the SX1211
As described below, only one interface can be selected at a time with NSS_CONFIG having the priority:
Rev 8 – February 2013
Page 35 of 92
www.semtech.com
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